computer organization and architecture

11. Fetch Operands (FO), Fetch Instruction (FI), Execute (E) calculated effective address (EA), Decode Instruction (DI) and Store Result (SR) are steps taken by CPU control to execute an instruction. Which of the following specifies a valid sequence of these steps:
CPU द्वारा किसी instruction को execute करने के लिए FO, FI, E, EA, DI और SR चरणों का सही क्रम क्या है?
(RPSC Computer Science 2016 Paper-I)
A. EA → FI → DI → FO → E → SR
B. EA → FO → FI → DI → E → SR
C. FI → DI → EA → FO → E → SR
D. DI → EA → FO → FI → E → SR

Correct Answer: C

Explanation (EN): Correct sequence is FI → DI → EA → FO → E → SR.

Explanation (HI): सही क्रम है: FI → DI → EA → FO → E → SR।

12. Considering equal processing time for each segment, speed-up S achieved by a K segment instruction pipeline operating on a straight sequence of N instruction is given by:
यदि प्रत्येक सेगमेंट का प्रोसेसिंग समय समान हो, तो K-सेगमेंट पाइपलाइन द्वारा N इंस्ट्रक्शन पर प्राप्त स्पीड-अप क्या होगा?
(RPSC Computer Science 2016 Paper-I)
A. (K(N-K))/(K+N-1)
B. (K+N)/KN
C. K(N+1)/(K+1)
D. KN/(K+N-1)

Correct Answer: D

Explanation (EN): Speedup formula is KN/(K+N-1).

Explanation (HI): स्पीड-अप का सूत्र KN/(K+N-1) होता है।

13. Which of the following type of Data Hazard in pipelined processor is harmless hazard?
पाइपलाइन प्रोसेसर में निम्न में से कौन सा डेटा हैज़र्ड हानिरहित होता है?
(RPSC Computer Science 2016 Paper-I)
A. Read after Write (RAW)
B. Read after Read (RAR)
C. Write after Write (WAW)
D. Write after Read (WAR)

Correct Answer: B

Explanation (EN): RAR hazard does not affect correctness.

Explanation (HI): RAR हैज़र्ड में डेटा नहीं बदलता इसलिए यह हानिरहित है।

14. If FD denotes hardware that fetches and decode instructions then, which of the following best defines data path of processor?
यदि FD हार्डवेयर fetch और decode करता है, तो प्रोसेसर का data path क्या होगा?
(RPSC Computer Science 2016 Paper-I)
A. FD + Secondary Memory + Primary Memory
B. FD + ALU + Register File
C. FD + ALU + CU
D. FD + ALU + CU + Register File

Correct Answer: B

Explanation (EN): Data path includes ALU and register file.

Explanation (HI): डेटा पाथ में ALU और रजिस्टर शामिल होते हैं।

15. _______ is not included in an instruction cycle of computer processor.
निम्न में से कौन instruction cycle का भाग नहीं है?
(RPSC Computer Science 2016 Paper-I)
A. Fetch and decode instruction
B. Handle an interrupt
C. Calculate effective address and fetch data
D. Execute instruction and store results

Correct Answer: B

Explanation (EN): Interrupt handling is outside normal instruction cycle.

Explanation (HI): इंटरप्ट हैंडलिंग instruction cycle का हिस्सा नहीं है।

16. Which of the following is the full form of CISC?
निम्न में से CISC का पूरा नाम क्या है?
(BPSC TRE 3.0 Computer Science 22.07.2024)
A. Complex Instruction Sequential Compilation
B. Complex Instruction Set Computer
C. Computer Integrated Sequential Compiler
D. More than one of the above

Correct Answer: B

Explanation (EN): CISC stands for Complex Instruction Set Computer.

Explanation (HI): CISC का अर्थ Complex Instruction Set Computer है।

17. The technology that stores only the essential instructions on a microprocessors chip and thus enhances its speed is referred to as :
वह तकनीक जो केवल आवश्यक निर्देशों को माइक्रोप्रोसेसर चिप में रखती है और गति बढ़ाती है, क्या कहलाती है?
(KVS PGT Computer Science 2017)
A. MIMD
B. CISC
C. RISC
D. SIMD

Correct Answer: C

Explanation (EN): RISC uses reduced instruction set to improve speed.

Explanation (HI): RISC कम इंस्ट्रक्शन सेट उपयोग कर गति बढ़ाता है।

18. In a well-tuned pipeline machine with five stages, after how many clock cycles one-one instruction rolls out every clock cycle assuming that all the stages take the same amount of time?
5-स्टेज पाइपलाइन में steady state के बाद हर clock cycle में एक instruction कब निकलता है?
(Haryana PGT Computer Science Assistant Professor 2024)
A. 1
B. 4
C. 5
D. 6

Correct Answer: B

Explanation (EN): Pipeline fills in (stages-1) cycles = 4.

Explanation (HI): पाइपलाइन 4 साइकल में भरती है।

19. After how many clock cycles, the second instruction will complete execution in a seven-stage pipeline machine?
7-स्टेज पाइपलाइन में दूसरा instruction कितने clock cycles में पूरा होगा?
(Haryana PGT Computer Science Assistant Professor 2024)
A. 1
B. 6
C. 7
D. 8

Correct Answer: D

Explanation (EN): Second instruction completes in 8 cycles.

Explanation (HI): दूसरा instruction 8 साइकल में पूरा होता है।

20. The instruction cycle time in a generic microprocessor is:
एक सामान्य माइक्रोप्रोसेसर में instruction cycle time क्या होता है?
(CGPSC Computer Science 2020)
A. Longer than the machine cycle time
B. Shorter than the machine cycle time
C. Same as the machine cycle time
D. Double the machine cycle time

Correct Answer: C

Explanation (EN): Instruction cycle can be treated equal to machine cycle in simplified cases.

Explanation (HI): सरल मामलों में instruction cycle = machine cycle माना जाता है।

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