computer organization and architecture

1. The mask logical micro operation is equivalent to which logical gate?
मास्क logical micro operation किस logical gate के समतुल्य है?
(DSSSB TGT C.S. 08.08.2021 (Shift-I))
A. OR gate
B. NOR gate
C. AND gate
D. NAND gate

Correct Answer: C

Explanation (EN): Masking in micro-operations is commonly done using the AND operation because it selectively keeps required bits and clears others.

Explanation (HI): Micro-operations में masking सामान्यतः AND operation से की जाती है क्योंकि यह आवश्यक bits को रखता है और बाकी को 0 कर देता है.

2. In ......... method, the word is written to the block in both the cache and main memory, in parallel.
उस विधि में word को cache और main memory दोनों में एक साथ लिखा जाता है।
(UGC NET C.S. June-2016 (Paper-III))
A. Write through
B. Write back
C. Write protected
D. Direct mapping

Correct Answer: A

Explanation (EN): In write through method data is written into the cache and the corresponding main memory location at the same time.

Explanation (HI): Write through method में data cache और corresponding main memory location दोनों में एक साथ लिखा जाता है.

3. What does the control unit generate to control other units?
अन्य units को नियंत्रित करने के लिए control unit क्या generate करती है?
(BPSC TRE 1.0 2023 (11-12))
A. Timing signals
B. Command signals
C. Control signals
D. More than one of the above

Correct Answer: C

Explanation (EN): The control unit generates control signals to direct the operation of other parts of the computer.

Explanation (HI): Computer के अन्य भागों के कार्य को नियंत्रित करने के लिए control unit control signals उत्पन्न करती है.

4. Which component of the computer is used to resolve the difference between CPU and the peripheral device?
CPU और peripheral device के बीच का अंतर किस component द्वारा resolve किया जाता है?
(DSSSB PGT C.S. M/F 11.07.2021)
A. Memory unit
B. Arithmetic Logic Unit
C. Interface unit
D. Control unit

Correct Answer: C

Explanation (EN): The interface unit acts as a bridge between CPU and peripheral devices and supervises input-output transfers.

Explanation (HI): Interface unit CPU और peripheral devices के बीच पुल की तरह कार्य करती है और input-output transfer को नियंत्रित करती है.

5. Which one of the following types of memory is fastest?
निम्न में से कौन-सी memory सबसे तेज होती है?
(UGC NET C.S. December-2022)
A. Cache Memory
B. Main Memory
C. Register Memory
D. Secondary Memory

Correct Answer: C

Explanation (EN): Register memory is the fastest memory and is located inside the CPU.

Explanation (HI): Register memory सबसे तेज memory होती है और CPU के अंदर स्थित होती है.

6. Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 40%
20 % and 40% respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered.
(Using the given frequencies the average unpipelined time is 44 ns and pipelined clock time becomes 11 ns. Hence speedup = 44/11 = 4 times.)
A. 10 nsec clock cycle वाली unpipelined machine में ALU और branch के लिए 4 cycles तथा memory operation के लिए 5 cycles लगते हैं। Relative frequencies 40%
B. 20% और 40% हैं। Pipeline overhead 1 nsec होने पर speedup कितना होगा?
C. 2 times
D. 4 times

Correct Answer: 6 TIMES

Explanation (EN): 8 times

Explanation (HI): b

7. In a memory hierarchy access time, hit ratio pairs for cache, main and virtual memory are given by (5ns, 80%), (100ns, 99.5%) and (10ms, 100%) respectively. The closest value of average access time of hierarchy is :
Memory hierarchy में cache
(10008 ns)
A. main memory और virtual memory के access time-hit ratio क्रमशः (5ns
B. 80%)
C. (100ns
D. 99.5%) और (10ms

Correct Answer: 100%) हैं। AVERAGE ACCESS TIME का निकटतम मान क्या होगा?

Explanation (EN): 98

Explanation (HI): 10024 ns

8. How is the TLB typically organized?
TLB सामान्यतः किस प्रकार संगठित होती है?
(BPSC TRE 3.0 Exam-22.07.2024 (11-12))
A. As a direct-mapped cache
B. As an associative cache
C. As a set-associative cache
D. More than one of the above

Correct Answer: B

Explanation (EN): TLB is typically organized as an associative cache because any virtual page can map to any entry.

Explanation (HI): TLB सामान्यतः associative cache के रूप में संगठित होती है क्योंकि कोई भी virtual page किसी भी entry में map हो सकता है.

9. ____ memory is intended to give memory speed approaching that of the fastest memories available
and at the same time provide a large memory size at the price of less expensive types of semiconductor memories.
(Cache memory का उद्देश्य सबसे तेज memory के करीब speed देना और कुल लागत कम रखना है.)
A. कौन-सी memory ऐसी होती है जो सबसे तेज memories के करीब speed देती है और साथ ही कम महँगी semiconductor memories की कीमत पर बड़ा memory size उपलब्ध कराती है?
B. Register
C. Counter
D. Flip flop

Correct Answer: CACHE

Explanation (EN): d

Explanation (HI): Cache memory is designed to provide speed close to the fastest memory while keeping overall cost lower.

10. A Series of statement explaining how the data is to be processed is called.
Data को कैसे process करना है यह बताने वाले statements की series को क्या कहते हैं?
(Bihar STET C.S. 18.09.2020 (Shift-I))
A. Editing
B. Compiler
C. Interpreter
D. Program

Correct Answer: D

Explanation (EN): A program is a series of statements or instructions written to process data or perform a task.

Explanation (HI): Program statements/instructions की एक श्रृंखला है जो data process करने या कोई कार्य करने के लिए लिखी जाती है.

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