1. Pipelining improves performance by: पाइपलाइनिंग प्रदर्शन को किस प्रकार बढ़ाती है? (UGC NET Computer Science June-2016 Paper-II)
A. decreasing instruction latency
B. eliminating data hazards
C. exploiting instruction level parallelism
D. decreasing the cache miss rate
Correct Answer: C
Explanation (EN): Instruction pipelining implements instruction level parallelism to increase CPU throughput.
Explanation (HI): पाइपलाइनिंग इंस्ट्रक्शन लेवल पैरेललिज्म का उपयोग करके CPU की गति बढ़ाती है।
2. Correct the order of instruction cycle: A. Read the effective address B. Fetch the information C. Execute the instruction D. Decode the instruction Choose the correct answer from the options given below : इंस्ट्रक्शन साइकिल का सही क्रम निर्धारित करें: A. Read the effective address B. Fetch the information C. Execute the instruction D. Decode the instruction नीचे दिए गए विकल्पों में से सही उत्तर चुनें: (UGC NET Computer Science December-2024)
A. A, B, C, D
B. B, D, A, C
C. B, A, D, C
D. A, B, D, C
Correct Answer: B
Explanation (EN): Correct order is Fetch → Decode → Read effective address → Execute.
3. Move the Read/Write head of disk in or out to position on a correct track is known as _____. डिस्क के रीड/राइट हेड को सही ट्रैक पर ले जाने की प्रक्रिया क्या कहलाती है? (DSSSB TGT Computer Science 01.08.2021 Shift-I)
A. Waiting time
B. Access time
C. Seek time
D. Latency time
Correct Answer: C
Explanation (EN): Seek time is the time taken to move the disk head to the desired track.
Explanation (HI): Seek time वह समय है जिसमें हेड सही ट्रैक पर पहुंचता है।
4. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor? 32-बिट प्रोसेसर (16-बिट डेटा बस, 8 MHz क्लॉक, 4 क्लॉक साइकल बस) की अधिकतम डेटा ट्रांसफर दर क्या है? (UGC NET Computer Science June-2015 Paper-III)
A. 8×10^6 bytes/sec
B. 4×10^6 bytes/sec
C. 16×10^6 bytes/sec
D. 4×10^9 bytes/sec
Correct Answer: B
Explanation (EN): Bus cycle rate = 8/4 = 2 MHz and each cycle transfers 2 bytes so rate = 4×10^6 bytes/sec.
Explanation (HI): बस साइकिल 2MHz और प्रति साइकिल 2 बाइट → कुल 4×10^6 बाइट/सेकंड।
5. The CPU a system having 1 MIPS execution needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device in attached to the system while CPU executes the background programs continuously. What is the maximum I/O data transfer rate if programmed I/O data transfer technique is used? CPU प्रणाली (1 MIPS, 4 मशीन साइकिल, 50% मेमोरी उपयोग) में अधिकतम I/O डेटा ट्रांसफर दर क्या है? (UGC NET Computer Science June-2015 Paper-III)
A. 500 Kbytes/sec
B. 2.2 Mbytes/sec
C. 125 Kbytes/sec
D. 250 Kbytes/sec
Correct Answer: D
Explanation (EN): Calculated I/O transfer rate = 250 Kbytes/sec.
Explanation (HI): अधिकतम I/O ट्रांसफर दर 250 Kbytes/sec होती है।
6. In most general case, the computer needs to process each instruction with the following sequence of steps: (A) Calculate the effective address (B) Execute the instruction (C) Fetch the instruction from memory (D) Fetch the operand from memory (E) Decode the instruction Choose the correct answer from the options given below : कंप्यूटर द्वारा इंस्ट्रक्शन प्रोसेस करने का सही क्रम क्या है? (UGC NET Computer Science December-2023)
A. (A), (B), (C), (D), (E)
B. (A), (B), (C), (E), (D)
C. (C), (E), (A), (D), (B)
D. (C), (E), (D), (A), (B)
Correct Answer: C
Explanation (EN): Correct order is Fetch → Decode → Address → Operand → Execute.
7. The sequence of events that happen during a typical fetch operation is/are : A. Memory B. MBR C. MAR D. PC E. IR Choose the correct order from the options given below : फेच ऑपरेशन के दौरान घटनाओं का सही क्रम क्या है? (UGC NET Computer Science December-2022)
A. A, B, C, D, E
B. D, C, A, B, E
C. E, D, C, B, A
D. D, C, A, E, B
Correct Answer: B
Explanation (EN): Correct order is PC → MAR → Memory → MBR → IR.
Explanation (HI): सही क्रम: PC → MAR → Memory → MBR → IR।
8. The correct sequence in fetch-execute cycle is A. Decode B. Fetch C. Execute Choose the correct answer from the following Fetch-execute साइकिल का सही क्रम क्या है? (UGC NET Computer Science December-2022)
A. A-B-C
B. B-C-A
C. C-B-A
D. B-A-C
Correct Answer: D
Explanation (EN): Correct order is Fetch → Decode → Execute.
Explanation (HI): सही क्रम है: Fetch → Decode → Execute।
9. Which of the following statements are correct? A. The first three-address instruction in the intermediate code is a leader. B. The instruction which is exactly at the middle of the given three address code is a leader. C. Any instruction that is the target of a conditional or unconditional jump is a leader. D. Any instruction that immediately follows a conditional or unconditional jump is a leader. Choose the correct answer from the options given below : निम्नलिखित में से कौन से कथन सही हैं? A. इंटरमीडिएट कोड का पहला three-address instruction एक leader होता है। B. दिए गए three-address code के बिल्कुल बीच वाला instruction leader होता है। C. कोई भी instruction जो conditional या unconditional jump का target होता है, वह leader होता है। D. कोई भी instruction जो conditional या unconditional jump के तुरंत बाद आता है, वह leader होता है। (UGC NET Computer Science December-2022)
A. A, B and C
B. B, C and D
C. A, C and D
D. A, B, C and D
Correct Answer: C
Explanation (EN): Leaders include first instruction, jump targets, and instructions after jumps.
Explanation (HI): लीडर में पहला instruction, jump का target और jump के बाद वाला instruction शामिल होता है।
10. Which of the following is not a characteristics of reduced instruction set (RISC)? निम्न में से कौन सा Reduced Instruction Set Computer (RISC) की विशेषता नहीं है? (RPSC Computer Science 2016 Paper-I)
A. Hardwired control
B. Relatively few addressing modes
C. Memory access limited to load and store
D. Variable length instruction formats
Correct Answer: D
Explanation (EN): RISC uses fixed-length instructions, not variable.
Explanation (HI): RISC में fixed-length instruction होते हैं, variable length नहीं।
